The present invention relates to methods and apparatus for polishing substrates using chemical mechanical polishing (“CMP”), more specifically, conformable CMP polishing of semiconductor wafers or tiles, semiconductor on insulator substrates, or semiconductor on glass substrates.
CMP processes and equipment have been employed in polishing substrates such as semiconductor wafers for use as substrates for solid state electronic devices. High electrical performance semiconductor on insulator (SOI) technology, an engineered multilayer semiconductor substrate, has been employed for high performance thin film transistors, CPU's, and may be used for solar cells, and flat panel displays, such as active matrix liquid crystal (AMLCD) and organic light emitting diode (AMOLED) displays. SOI structures or substrates include a thin layer of substantially single crystal semiconductor material on an insulating semiconductor material. For example, an SOI substrate may include a thin single crystal silicon layer on an insulating amorphous or polycrystalline silicon material. A less expensive glass or glass-ceramic material may be used to form the insulating or handle substrate in place of the much more expensive semiconductor material, thereby producing a single crystal silicon (or other single crystal semiconductor material) on glass “SOG” substrates suitable for displays, sensors, photovoltaics, solar cells and other applications.
SOG substrates may be considered a subset of SOI substrates. Unless otherwise expressly stated or described herein, all descriptions of SOI products and processes contained herein are intended to include SOG products and processes as well as other types of SOI products and processes.
One way of obtaining the thin semiconductor layers required for SOI structures is epitaxial growth of silicon (Si) on lattice matched substrates. An alternative process includes the bonding of a single crystal silicon wafer to another silicon wafer on which an oxide layer of SiO2 has been grown, followed by polishing or etching of the top wafer down to, for example, a 0.05 to 0.3 micron layer of single crystal silicon. Further methods include ion-implantation of ions, such as hydrogen, helium or oxygen ions, to either (a) form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation, or (b) form a weakened layer in the silicon donor wafer in order to separate (exfoliate) a thin Si layer for film from the donor wafer in the case of hydrogen or helium ion implantation. Such processes have been used to separate a thin layer or film of silicon or other semiconductor material from a donor wafer and transfer the thin film to a handle or insulating substrate to produce an SOI substrate. Such processes are referred to herein as “ion implantation thin film transfer processes” or simply “thin film transfer processes.”
Several methods have been employed to separate the thin layer or film from the donor wafer in ion implantation thin film transfer processes and bond the silicon layer to an insulating substrate. U.S. Pat. Nos. 5,374,564 and 6,013,563 disclose a thermal bonding and separation thin film transfer process for producing SOI substrates, in which an ion implanted single crystal silicon donor wafer is brought into contact with a surface of an insulating semiconductor substrate or handle wafer. Heat, e.g. thermal energy, is then applied to thermally bond the donor wafer to the handle wafer and separate a thin layer of silicon from the donor wafer, thereby leaving a thin film of single crystal silicon (or other single crystal semiconductor material) thermally bonded to the handle wafer. U.S. Pat. No. 7,176,528 discloses an anodic bonding and separation ion implantation thin film transfer process for producing SOG substrates, in which an ion implanted single crystal silicon donor wafer is brought into contact with a surface of an insulating glass or glass ceramic substrate. Heat and voltage are applied to the wafer and the glass substrate (pressure may also be applied) to anodically bond the wafer to the glass substrate and separate a thin layer of silicon from the wafer, thereby leaving a thin film of single crystal silicon (or other single crystal semiconductor material) anodically bonded to the glass substrate.
After the removal of a first thin layer or film of silicon (or other semiconductor material) from the donor semiconductor wafer in an SOG process, which may remove only a 200 nanometer to 800 nanometer layer of material, about 99% or more of the donor semiconductor wafer remains. Due to the relatively high cost of single crystal silicon and other semiconductor materials, it is desirable to re-use the remaining portion of the donor wafer as many times as possible to reduce material costs. Large area SOI structures may be produced by arraying a plurality of laterally disposed individual rectangular donor wafers (or “tiles”) on a single insulating substrate (such as a display grade sheet of glass or glass-ceramic material), separating a plurality of thin rectangular semiconductor layers from the tiles, and bonding the layers to the insulating substrate (a process referred to herein as “tiling”). Use of a plurality of donor wafers or tiles multiplies the economic savings achievable through re-use of the donor wafers.
After separation of a layer from a donor semiconductor wafer in an ion implantation thin film transfer process, the exfoliated or cleaved surface of the donor wafer and of the SOI substrate includes residual ions from the implantation process and crystalline damage from the implantation and separation process. In order to re-use a donor semiconductor wafer, it is necessary to refinish or refresh the wafer by curing or removing the exfoliated surface to return it to a relatively damage-free and ion contamination free state. Similarly, in order to provide the resulting SOI substrate with the desired electrical properties, it is necessary to refresh or remove the ion contaminated and damaged outer layer of the exfoliated surface of the SOI substrate. This ion contaminated and damaged outer layer of the donor wafer and of the SOI substrate has been removed using conventional CMP techniques. While CMP techniques are well documented and existing equipment may be readily obtained, there are a number of drawbacks with the existing CMP technology in the context of semiconductor re-use in ion implantation thin film transfer processes.
FIG. 1 is a diagrammatic illustration of a conventional chemical, mechanical polishing (“CMP”) setup, in which a workpiece 1 is mounted on a carrier or polishing head 3 using a vacuum/suction or surface tension. An exposed surface of the wafer is pressed against a polishing pad 5, which may be a standard pad or a fixed-abrasive pad, mounted on a rigid turn table 7 to create relative motion between the abrasive pad and the wafer. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. A polishing slurry, including a chemically-reactive agent (and abrasive particles if a standard pad is used) is applied to the surface of the polishing pad. The carrier head provides a controllable load, i.e., pressure, on the substrate 1 to push it against the polishing pad 5. In order to achieve a more uniform polishing across the surface of the wafer, mechanisms may be provided in the polisher head to apply uniform pressure on the back surface of the wafer and a reciprocating, oscillating or orbital motion may be provided between the polisher head 3 and the turn table. CMP processes provide a high polishing rate and a resulting flat planar substrate surface that is free of significant large scale surface topography (e.g. substantially planar/flat) and small-scale surface roughness (e.g. substantially smooth).
As shown in FIG. 1, conventional CMP processes apply the polishing pressure to the back surface of a relatively rigid workpiece having a finite modulus of elasticity (e.g. the semiconductor donor wafer in the case of SOI fabrication processes). This method of pressure application results in a non-uniform pressure distribution across the wafer surface. Line A in FIG. 2 plots the results of a finite element analysis of the pressure distribution across a round wafer during polishing in a conventional CMP system. As can be seen in FIG. 2, the polishing pressure is highest in the middle and decreases to zero at the wafer edges. This uneven pressure distribution results in non-uniform material removal across the wafer surface which affects the flatness of the polished wafer. The flatness or planarity requirements of the semiconductor donor wafers used for SOI applications are stringent and are typically in the range of less than 5 μm (5000 nm) variations in amplitude and over 20 mm in pitch, e.g. distance from peak to peak.
As a result of the non-uniform material removal with conventional CMP processes, an excess amount of material must be removed from the exfoliated surface of the donor wafer to adequately refresh the surface of the donor wafer for reuse with convention CMP processes. For example, if 0.150 microns (150 nm) of actual damage and contamination needs to be removed from the exfoliated surface of a donor wafer, then to be certain that the damage and contaminated layer has been completely removed from the whole surface of the donor wafer, taking into account the aforementioned non-uniform characteristics of the CMP protocols, at least 1.0 micron (1000 nm) may need to be removed from the donor wafer. Thus, over six times the thickness of the actual damage may need to be removed in order to ensure that all the damage and contamination is removed, which is highly wasteful and has significant negative cost implications.
Conventional CMP processes may exhibit particularly poor results when polishing non-round semiconductor wafers or SOI substrates having sharp corners, such as rectangular donor wafers or tiles, as may be employed when tiling to produce large area SOI and SOG substrates. The aforementioned non-uniform material removal is amplified at the corners of rectangular donor wafers due to higher polishing speed and non-uniform polishing pressure at these locations, which result in faster material removal at the corners of the wafer compared with the center of the wafer. This is know as the “pillow” or “pillowing effect,” because the rectangular donor wafer takes on a non-planar pillow-like shape with reduced thickness at the corners compared to the central region of the rectangular donor wafers or tiles. Multiple re-uses of rectangular donor wafers by such CMP protocols multiplies the pillow effect, resulting in the premature end to a given wafer's re-use life cycle as the surface geometry (especially near the corners) diverges from acceptable re-use functional limits as result of the pillowing effect. Thus, the number of times a rectangular wafer can be effectively re-used employing conventional CMP techniques is limited. Therefore, there is a need for a process of refinishing or refreshing the surface of semiconductor donor wafers, especially rectangular semiconductor donor tiles, that increases the number of times that a donor wafer or donor tile may be reused in an ion implantation thin film transfer SOI fabrication process.
Conventional planarizing CMP processes and equipment are also often unsatisfactory for polishing of substrates with very thin layers thereon, such as SOI substrates. FIG. 3 (not drawn to scale) diagrammatically illustrates an SOG substrate 11 that maybe used, for example, as a backplane substrate for liquid crystal display (LCD) or organic light emitting diode (OLED) display panels, sensors, photovoltaics, solar cells, etc.
An SOG substrate includes an insulating substrate of glass or glass ceramic 13. Glass or glass-ceramic substrates typically have relatively large variations in surface topography as compared to a semiconductor wafer in an SOI process and as compared to the thin semiconductor layer on an SOG substrate. For example, as illustrated in FIG. 3, a glass substrate may have large scale or macro surface variations or undulations with high spots 17 and low spots 19 that may have an amplitude of about 20 μm (20000 nm). Whereas the semiconductor layer 15 on the glass substrate 13 is a very thin layer or layers of material that conforms to the macro surface topography of the glass substrate surface. These thin semiconductor layers or films typically have a thickness on the order of several hundreds of nanometers thick, which is thinner by many orders of magnitude than the amplitude of the macro surface topography variations of the underlying glass substrate of 20000 nanometers. For example, a semiconductor layer 15 having an initial thickness of about 420 nm may be transferred from a donor wafer onto the glass substrate in an ion implantation thin film transfer process. This “as transferred” layer must then be thinned to remove the ion contaminated and damaged outer layer and thin the layer down to the desired final thickness of about 200 nm by removing about 220 nm of material. Thus, the 20 μm (20000 nm) variations in surface topography of the underlying substrate is about a hundred times larger than the 200 nm thickness of the final Si layer 7 and the 220 nm layer of material that must be removed in order to obtain the desired final 200 nm layer thickness.
When conventional planarizing CMP polishing techniques are employed to thin an as deposited silicon layer 17 on an SOI substrate 11, the entire as deposited silicon layer is often unacceptably removed from the high spots 17 of the large scale undulations on the insulating glass substrate 13. For example, if an SOG substrate 11 were thinned down to the plane designated by line P in FIG. 3, then the entire silicon layer 15 would be removed from the high spots 17 of the undulations in the surface of the glass, thus creating holes through the silicon layer 15. Yet, the damaged and contaminated top layer of the as transferred silicon layer 15 may remain untouched and un-thinned over the low spots 19. In order to avoid removing entire portions of the layer(s) and creating holes in the layer(s), the finishing apparatus should compensate for or conform to the undulating surface of the thin film 15 while removing material therefrom, such that material is substantially uniformly removed across the surface of the film. Commonly owned pending Published U.S. Application 2008/0299871A1 discloses a conformable polishing apparatus.
Conventional CMP techniques are also relatively expensive. A conventional CMP set-up includes a rotating polishing pad (having certain abrasive characteristics), a slurry (also having certain abrasive characteristics), and a rotating chuck or head to press the semiconductor wafer against the polishing pad and slurry. In order to obtain a semiconductor wafer with satisfactory surface characteristics in a re-use or as transferred layer thinning context, multiple equipment set-ups are required. For example, multiple polishing pads of varying aggressiveness may be required. This requires either a manual process steps to change the polishing pad on a given piece of equipment, or multiple pieces of equipment each with a different polishing pad. Either approach adds equipment cost and cycle time to the manufacturing process and adversely impacts the commercial viability of the SOI substrates in end-use applications. Furthermore, the workpieces must be loaded one at a time into the polishing head.
In an ion implantation thin film transfer process, the final cost of the SOI product and of products made with SOI substrates is driven by the ability to (a) efficiently and economically thin and finish the SOI substrates and (b) re-use (e.g. refresh or refinish) the donor semiconductor wafers many times. Accordingly, there is a need for an efficient and effective “conformable” polishing process for thinning the as transferred thin film on an SOI or SOG substrate in an ion implantation thin film transfer process and other thin film fabrication processes. There is also a need for refreshing the donor semiconductor wafer, especially rectangular semiconductor donor tiles, as many times as possible. There is also a need for an efficient and affordable continuous process for thinning and finishing a plurality of donor wafers and/or SOI substrates for the economical commercial mass production of SOI substrates.